Boundary-scan design principles for efficient LSSD ASIC testing
IBM Journal of Research and Development
At-speed delay testing of synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Test methodologies and design automation for IBM ASICs
IBM Journal of Research and Development
Analysis and Detection of Timing Failures in an Experimental Test Chip
Proceedings of the IEEE International Test Conference on Test and Design Validity
Detecting Delay Flaws by Very-Low-Voltage Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Testing the Enterprise IBM System/390TM Multi Processor
Proceedings of the IEEE International Test Conference
Test Application Timing: The Unexplored Issue in AC Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Delay Test: The Next Frontier for LSSD Test Systems
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
IEEE Design & Test
Fastpath: a path-delay test generator for standard scan designs
ITC'94 Proceedings of the 1994 international conference on Test
Standard-cell-based design methodology for high-performance support chips
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
A new IEEE 1149.1 boundary scan design for the detection of delay defects
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Enhanced Reduced Pin-Count Test for Full-Scan Design
Journal of Electronic Testing: Theory and Applications
System-on-Chip Testability Using LSSD Scan Structures
IEEE Design & Test
Comparing Functional and Structural Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Building Block BIST Methodology for SOC Designs: A Case Study
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Contactless Digital Testing of IC Pin Leakage Currents
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Enhanced Reduced Pin-Count Test for Full-Scan Design
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test Support Processors for Enhanced Testability of High Performance Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Distributed Diagnosis of Interconnections in SoC and MCM Designs
Journal of Electronic Testing: Theory and Applications
Testing Gbps Interfaces without a Gigahertz Tester
IEEE Design & Test
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A DLL design for testing I/O setup and hold times
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
This paper describes a novel design-for-test (DFT) conceptfor I/O delay testing while contacting very few pads,using boundary scan and new test-generation software. Inproduction testing of the IBM System/390 Generation 3驴and several ASIC chips, these patterns uncovered uniquemanufacturing defects.