When zero picoseconds edge placement accuracy is not enough
Proceedings of the IEEE International Test Conference 2001
Delay test of chip I/Os using LSSD boundary scan
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Complete, Contactless I/O Testing " Reaching the Boundary in Minimizing Digital IC Testing Cost
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Practices in Mixed-Signal and RF IC Testing
IEEE Design & Test
A DLL design for testing I/O setup and hold times
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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These authors from Intel provide evidence for the rapid deployment of ICs equipped with high-speed serial interfaces. They argue that this constitutes a revolutionary functional and design paradigm shift, which in turn dictates a corresponding shift in test and DFT methods. They also review various approaches and discuss the tradeoffs they experienced in testing actual devices.