Status of IEEE Testability Standards 1149.4, 1532 and 1149.6
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Testing Gbps Interfaces without a Gigahertz Tester
IEEE Design & Test
Embedded System Level Self-Test for Mixed-Signal IO Verification
Journal of Electronic Testing: Theory and Applications
An embedded 1149.4 extension to support mixed-signal debugging
Microelectronics Journal
A DLL design for testing I/O setup and hold times
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Embedded test of memory and random logic can enable very low cost ATE to test large, high speed ICs because high quality at-speed tests can be generated on-chip. However, it is also necessary to test the DC and AC parameters of the input/output (I/O) circuitry. This paper describes how most I/O pin characteristics can be tested cost-effectively with a variety of novel techniques that exploit the 1149.1 and 1149.4 test standards. The techniques measure VOL/IOL, VOH/IOH, VIH, and VIL at DC, perform at-speed I/O wrap, and test on-chip powerrail impedance, all via minimum pin-count (MPC) access. The 1149.4 bus is also suitable, of course, for testing mixed-signal functions. The paper then discusses costs and benefits of MPC testing of high pin-count ICs on low cost tester to show that testing costs can be reduced to insignificance.