Journal of Electronic Testing: Theory and Applications - Joint special issue on analog and mixed-signal testing
Journal of Electronic Testing: Theory and Applications
Testing the Integrity of the Boundary Scan Test Infrastructure
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
An IEEE 1149.1 Based Logic/Signature Analyzer in a Chip
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
P1149.4-Problem or Solution for Mixed-Signal IC Design?
Proceedings of the IEEE International Test Conference
Control and Observation of Analog Nodes in Mixed-Signal Boards
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Complete, Contactless I/O Testing " Reaching the Boundary in Minimizing Digital IC Testing Cost
ITC '02 Proceedings of the 2002 IEEE International Test Conference
IEEE 1149.4 Compatible ABMs for Basic RF Measurements
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On-Chip Mixed-Signal Test Structures Re-used for Board Test
ITC '04 Proceedings of the International Test Conference on International Test Conference
Reliability and availability in reconfigurable computing: a basis for a common solution
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Current State of the Mixed-Signal Test Bus 1149.4
Journal of Electronic Testing: Theory and Applications
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Debugging electronic circuits is traditionally done with bench equipment directly connected to the circuit under debug. In the digital domain, the difficulties associated with the direct physical access to circuit nodes led to the inclusion of resources providing support to that activity, first at the printed circuit level, and then at the integrated circuit level. The experience acquired with those solutions led to the emergence of dedicated infrastructures for debugging cores at the system-on-chip level. However, all these developments had a small impact in the analog and mixed-signal domain, where debugging still depends, to a large extent, on direct physical access to circuit nodes. As a consequence, when analog and mixed-signal circuits are integrated as cores inside a system-on-chip, the difficulties associated with debugging increase, which cause the time-to-market and the prototype verification costs to also increase. The present work considers the IEEE1149.4 infrastructure as a means to support the debugging of mixed-signal circuits, namely to access the circuit nodes and also an embedded debug mechanism named mixed-signal condition detector, necessary for watch-/breakpoints and real-time analysis operations. One of the main advantages associated with the proposed solution is the seamless migration to the system-on-chip level, as the access is done through electronic means, thus easing debugging operations at different hierarchical levels.