An Application of Photoconductive Switch for High-Speed Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference
Delay test of chip I/Os using LSSD boundary scan
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Alternative interface methods for testing high speed bidirectional signals
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A performance analysis system for MEMS using automated imaging methods
ITC '98 Proceedings of the 1998 IEEE International Test Conference
High speed testing-have the laws of physics finally caught up with us?
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Timing Analyzer for Embedded Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Microelectromechanical systems (MEMS) tutorial
ITC '98 Proceedings of the 1998 IEEE International Test Conference
IEEE Design & Test
A test system architecture to reduce transmission line effects during high speed testing
ITC'94 Proceedings of the 1994 international conference on Test
Challenges and directions for testing IC
Integration, the VLSI Journal
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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A solution for testing fast-switching bidirectionalsignal lines using an array of technology-specifictransceivers is described in [1]. This method uses an activecomponent located between the device-under-test (DUT)and the automated test equipment (ATE) to reduce electricalinterconnect delays to less than 150ps.In this paper, the transceiver array concept isextended to include higher-level test processes such as real-timealgorithmic pattern generation (APG), multi-gigahertzsignal multiplexing, and others. The active test componentis therefore called a "Test Support Processor" (TSP). Itgreatly reduces the functionality and performance capabilityrequired of the ATE, while maintaining signal integrity, andimproving overall test quality.In its minimum configuration, the TSP provides anarray of technology-specific transceivers very close to theDUT, as described in [1]. This reduces transmission lineeffects, allowing for at-speed test of fast I/O switchingcharacteristics. This technique may lead to lower-cost,higher-speed ATE by simplifying and standardizing the pinelectronics.Beyond the minimum configuration, higher-leveltest processes may be included in the TSP, depending uponthe DUT test requirements. The TSP is specifically intendedto complement and support existing DFT and BISTstructures within the DUT. In some applications it may bepossible to reduce BIST overhead by off-loading testfunctionality to the TSP, thereby reducing recurring siliconcosts.The use of the TSP provides an additional degreeof freedom for partitioning the test problem, and may resultin a significant paradigm shift for future ATE architectures.The TSP represents an economic alternative to (projected)$50M ATE and/or over-application of built-in self-test(BIST) techniques (i.e. where silicon area is very limited).This paper describes variations of the TSP concept,its potential applications, and economic impact. Threevariations are illustrated through prototype demonstrations,including: (A) a 2.67Gbps test pattern source, (B) atransceiver array for testing a high speed 4Mbit SRAM, and(C) a reconfigurable real-time APG for memory testing,implemented using a field-programmable gate array(FPGA).