Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A method for generating weighted random test pattern
IBM Journal of Research and Development
Built-in self-test support in the IBM engineering design system
IBM Journal of Research and Development
Test methodologies and design automation for IBM ASICs
IBM Journal of Research and Development
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Addressing Early Design-For-Test Synthesis in a Production Environment
Proceedings of the IEEE International Test Conference
Delay test of chip I/Os using LSSD boundary scan
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Designing for scan test of high performance embedded memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Integrating Logic BIST in VLSI Designs with Embedded Memories
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Test Structure Verification of Logical BIST: Problems and Solutions
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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System-on-Chip designs use numerous and diverseembedded cores and memories. V ery high system reliability requirements mandate greater than 99.9% ATPGchip manufacturing test coverage. Logic BIST andMemory BIST are increasingly used for high systemtest coverage with additional constraints that somecores or pockets of user designed logic have to be functionally active during BIST. This paper will describethe challenges of a design methodology to handle suchSOC designs and the automated solutions that addressthese problems.