Logic testing and design for testability
Logic testing and design for testability
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Built-in self-test support in the IBM engineering design system
IBM Journal of Research and Development
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Building Block BIST Methodology for SOC Designs: A Case Study
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A BIST Pattern Generator Design for Near-Perfect Fault Coverage
IEEE Transactions on Computers
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Test Structure Verification (TSV) is the process used to assess the conformance of a circuit to a set of predefined Design For Testability (DFT) rules. Test generation algorithms are typically optimized for circuits that are highly testable, so Test Structure Verification (TSV)ultimately indicates the overall testability of a circuit.Logical BIST (Built In Self Test) is a methodology basedon signature analysis which produces patterns used to verify the correctness of the manufactured circuit via specially designed BIST hardware. This paper describes aset of proven production level procedures used to identifyand verify the test structure and behavior of BIST hardware. These algorithms are based on the TSV implementation of IBM's TestBench test generation system.