Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A Data Compression Technique for Built-In Self-Test
IEEE Transactions on Computers
Optimal Robust Compression of Test Responses
IEEE Transactions on Computers
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
IEEE Transactions on Computers
Test response compaction for built-in self testing
Test response compaction for built-in self testing
System-on-a-Chip: Design and Test
System-on-a-Chip: Design and Test
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
High Assurance Software Testing In Business And DOD
Journal of Integrated Design & Process Science
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The realization of space-efficient support hardware for built-in self-testing (BIST) is of great importance in the design and manufacture of VLSI circuits. Novel approaches to designing aliasing-free space compaction hardware were recently proposed in the context of testing cores-based system-on-chip (SOC) for single stuck-line faults, extending the well-known concepts of conventional switching theory, specifically those of cover table and frequency ordering commonly utilized in the simplification of switching functions, and of compatibility relation as used in the minimization of incomplete sequential machines, based on optimal generalized sequence mergeability, as developed and utilized by the authors in earlier works. The advantages of these aliasing-free compaction methods over earlier techniques are quite obvious, since zero-aliasing is achieved without any modifications of the module under test (MUT), while keeping the area overhead and signal propagation delay relatively low as contrasted with the conventional parity tree linear compactors. Besides, the approaches could be applied with both deterministic compacted and pseudorandom test patterns. The subject paper, without furnishing details of the different algorithms developed in the implementation of these approaches to designing zero-aliasing space compactors, provides the mathematical basis of selection criteria for merger of an optimal number of outputs of the MUT to achieve maximum compaction ratio in the design, along with some results from simulation experiments conducted on ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits, with simulation programs ATALANTA, FSIM, and HOPE.