A Data Compression Technique for Built-In Self-Test
IEEE Transactions on Computers
Optimizing error masking in BIST by output data modification
Journal of Electronic Testing: Theory and Applications
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
Test-set preserving logic transformations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Self-Checking Comparator with One Periodic Output
IEEE Transactions on Computers
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Space Compaction of Test Responses for IP Cores Using Orthogonal Transmission Functions
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
High-level test generation using physically-induced faults
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Test response compaction using multiplexed parity trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Shrinking wide compressors [BIST]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
| Hi-index | 14.98 |
Abstract--A structure-independent method for space compaction in combinational circuits based on a new generic scheme is presented in this paper. It is shown that a single-output compactor can always be designed for compressing test responses of a circuit-under-test (CUT) with guaranteed zero-aliasing. Test responses from multiple outputs are compacted to a single periodic data stream. The compactor is independent of the fault model and can be designed only from the knowledge of the given test set and the corresponding fault-free responses. An additional response logic and a special code checker are used to design the compactor. The same test set given for the CUT also detects all multiple stuck-at faults in the response logic and almost all faults in the rest of the compactor. Further, time compaction is also easily achieved. Since the design can be accomplished without any information about the structure and functionality of the CUT, it would be useful for testing embedded cores as their internal structures may not be transparent to the users.