Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Programmable BIST Space Compactors
IEEE Transactions on Computers
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
Effective diagnostics through interval unloads in a BIST environment
Proceedings of the 39th annual Design Automation Conference
On output response compression in the presence of unknown output values
Proceedings of the 39th annual Design Automation Conference
Test Resource Partitioning for SOCs
IEEE Design & Test
Extending OPMISR beyond 10x Scan Test Efficiency
IEEE Design & Test
Design of compactors for signature-analyzers in built-in self-test
Proceedings of the IEEE International Test Conference 2001
Packet-Based Input Test Data Compression Techniques
ITC '02 Proceedings of the 2002 IEEE International Test Conference
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Reducing Test Application Time Through Test Data Mutation Encoding
Proceedings of the conference on Design, automation and test in Europe
Testing High-Speed SoCs Using Low-Speed ATEs
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Synthesis of single-output space compactors for scan-based sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Space Compression Methods With Output Data Modification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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This paper presents a test resource partitioning technique based on an efficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor is a single-output compactor, high compaction ratios can be obtained even for chips with a small number of outputs. Some theorems for the design of q-Compactor are presented to achieve full diagnostic ability, minimize error cancellation and handle unknown bits in the outputs of the circuit under test (CUT). The q-Compactor can also be moved to the load-board, so as to compact the output response of the CUT even during functional testing. Therefore, the number of tester channels required to test the chip is significantly reduced. The experimental results on the ISCAS '89 benchmark circuits and an MPEG 2 decoder SoC show that the proposed compaction scheme is very efficient.