Low-power scan testing for test data compression using a routing-driven scan architecture

Authors:
Dong Xiang;Dianwei Hu;Qiang Xu;Alex Orailoglu
Affiliations:
School of Software, Tsinghua University, Beijing, China;School of Software, Tsinghua University, Beijing, China;Department of Computer Science and Engineering, Chinese University of Hong Kong, Shatin, NT, Hong Kong;Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2009

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Abstract

A new scan architecture is proposed to reduce peak test power and capture power. Only a subset of scan flip-flops are activated to shift test data or capture test responses in any clock cycle. This can effectively reduce the capture test power and peak test power. Two routing-driven schemes are proposed to reduce the routing overhead. Experimental results show that the proposed scan architecture can effectively reduce peak test power, capture power, test data volume, and test application cost.