Optimal Space Compaction of Test Responses

Testing ICs: Getting to the Core of the Problem

Computer

A Structural Method for Output Compaction of Sequential Automata Implemented as Circuits

WIA '99 Revised Papers from the 4th International Workshop on Automata Implementation

4.3 Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Space and Time Compaction Schemes for Embedded Cores

ITC '01 Proceedings of the 2001 IEEE International Test Conference