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Journal of Electronic Testing: Theory and Applications
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
Test pattern generation based on arithmetic operations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On minimizing aliasing in scan-based compaction
Journal of Electronic Testing: Theory and Applications
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IEEE Transactions on Computers
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ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Optimal Space Compaction of Test Responses
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Multiplicative Window Generators of Pseudo-random Test Vectors
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Test response compaction using arithmetic functions
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
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IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
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ITC '01 Proceedings of the 2001 IEEE International Test Conference
On Accumulator-Based Bit-Serial Test Response Compaction Schemes
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
BIST Technique by Equally Spaced Test Vector Sequences
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
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Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
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IEEE Transactions on Computers
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SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
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Adders, subtracters, and multipliers, which are available in many data paths, can be utilized to generate patterns and compact test responses. While previous work studied configurations which process patterns and test responses that have the size of a data word, this paper investigates bit serial pattern generators and compactors as they are required, for example, to test a random logic portion of the circuit by means of a scan path. Different arithmetic pattern generators are proposed that can produce a variety of bit strings with long periods and similar fault coverage as pseudorandom bit strings. The paper also analyzes aliasing in arithmetic compactors that process the test responses bit by bit. An upper bound on the limiting value of the aliasing probability for large test lengths can be computed very efficiently. The results of this paper open up a new range of applications for arithmetic BIST.