Test pattern generation based on arithmetic operations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
Microprocessor based testing for core-based system on chip
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Optimal hardware pattern generation for functional BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On applying the set covering model to reseeding
Proceedings of the conference on Design, automation and test in Europe
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
4.3 Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Non-Intrusive BIST for Systems-on-a-Chip
ITC '00 Proceedings of the 2000 IEEE International Test Conference
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Testing a System-On-a-Chip with Embedded Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On the Selection of Efficient Arithmetic Additive Test Pattern Generators
ETW '03 Proceedings of the 8th IEEE European Test Workshop
Software-based self-testing methodology for processor cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Response shaper: a novel technique to enhance unknown tolerance for output response compaction
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
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Built-in self-test (BIST) strategies require theimplementation of efficient test pattern generators (TPG) inorder to excite and observe the potential faults of thecircuit. Arithmetic additive TPGs (AdTPG) allow the reuseof existing internal datapaths to perform this operationwithout a penalty in the circuit area. As in pseudo-randomgenerators, AdTPGs need reseeding to efficiently coverhard-to-detect faults. The test vectors targeting hard-to-detectfaults are often difficult to be obtained from a simpleiterative addition operation.In this paper, a strategy to generate the reseeding for anAdTPG based on a standard ALU is presented. Themethodology benefits from the existence of don't-cares inthe test vectors and from the insertion of dummy vectors inthe test sequence. Thanks to this, a reduction of the memoryrequirements and the test length is achieved.