BIST Technique by Equally Spaced Test Vector Sequences
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
| Hi-index | 0.00 |
Arithmetic function modules which are available in many circuits can be utilized to generate test patterns and compact test responses. Recently, it was shown that an adder or an accumulator cannot be used as a bit serial test pattern generator due to the poor random properties of the generated sequences. Thus, accumulator-multiplier or adder-multiplier structures have been proposed. In this paper we show that an accumulator behaving, in testmode, as a Non-Linear Feedback Shift Register (NLFSR) can be used efficiently for bit serial test pattern generation. A hardware as well as a software implementation of the proposed scheme is given. The efficiency of the proposed scheme is verified by comparing it against LFSR and other arithmetic function based bit serial test pattern generators.