Accumulator Compression Testing
IEEE Transactions on Computers - The MIT Press scientific computation series
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
Test pattern generation based on arithmetic operations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Optimal hardware pattern generation for functional BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
4.3 Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Non-Intrusive BIST for Systems-on-a-Chip
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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New arithmetic two-dimensional generators of pseudo-random test vectors are presented. As an integral part of a recently proposed arithmetic built-in self test (ABIST) environment, all generation functions are executed by basic building blocks performing regular functions of data path architectures, yet the scheme is compatible with scan, parallel scan, partial scan and boundary scan designs. The need for extra hardware is either entirely eliminated or drastically reduced, test vectors can be easily distributed to different modules of the system, and there is virtually no performance degradation.