On the Yield of VLSI Processors with On-Chip CPU Cache
IEEE Transactions on Computers
Self-exercising self testing k-order comparators
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A cache-defect-aware code placement algorithm for improving the performance of processors
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Embedded RAIDs-on-chip for bus-based chip-multiprocessors
ACM Transactions on Embedded Computing Systems (TECS)
| Hi-index | 0.00 |