Strongly Code Disjoint Checkers
IEEE Transactions on Computers
Error-control coding for computer systems
Error-control coding for computer systems
On the Design of Combinational Totally Self-Checking 1-out-of-3 Code Checkers
IEEE Transactions on Computers
Low-cost protection for SER upsets and silicon defects
Proceedings of the conference on Design, automation and test in Europe
Journal of Electronic Testing: Theory and Applications
| Hi-index | 14.98 |
A typical self-checking circuit has an unordered code encoded output. The optimal scheme needs $\lceil\, {\rm log}\, (r + 1)\, \rceil$ check bits, where r is the number of unique weights in all output patterns. A hyper optimal scheme for self-checking output encoding is proposed in this paper where the number of check bits will be further reduced in some cases. Two algorithms are presented to search for the hidden m-out-of-n code words. The hidden m-out-of-n code words are found when all unique output patterns, specified by the circuit specification, in the n selected output bits have exactly m 1s. The output bits that belong to the hidden m-out-of-n code words are then excluded from further encoding. Typically, the number of added check bits of the proposed technique ranges from 0 to $\lceil\, {\rm log}\, (p + 1)\, \rceil$, where p驴r. When hidden m-out-of-n code words exist, applying the proposed scheme usually results in significant hardware cost and delay time reduction. In the five MCNC FSM benchmark circuits that have been identified with hidden m-out-of-n code words, 10% to 41% hardware reductions are exhibited compared to the theoretically optimal separable code encoding scheme. In addition, 7% to 45% reductions in checking delays are demonstrated for the same circuits compared to the separable code encoding scheme.