Optimal layout to avoid CMOS stuck-open faults
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults
Journal of Electronic Testing: Theory and Applications
Sensing circuit for on-line detection of delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High Speed VLSI Interconnections: Modeling, Analysis, and Simulation
High Speed VLSI Interconnections: Modeling, Analysis, and Simulation
Scheduling Policies for Fault Tolerance in a VLSI Processor
Proceedings of the The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
On-Line Testing Scheme for Clock's Faults
Proceedings of the IEEE International Test Conference
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
On-line detection of logic errors due to crosstalk, delay, and transient faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Scaling Deeper to Submicron: On-Line Testing to the Rescue
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Compact and Highly Testable Error Indicator for Self-Checking Circuits
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
An asynchronous totally self-checking two-rail code error indicator
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Embedded two-rail checkers with on-line testing ability
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Highly testable and compact single output comparator
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimization of error detecting codes for the detection of crosstalk originated errors
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Journal of Electronic Testing: Theory and Applications
Online Testing Approach for Very Deep-Submicron ICs
IEEE Design & Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Interactive presentation: Pulse propagation for the detection of small delay defects
Proceedings of the conference on Design, automation and test in Europe
Power consumption of fault tolerant busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing resistive opens and bridging faults through pulse propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 7th ACM international conference on Computing frontiers
Hard Data on Soft Errors: A Large-Scale Assessment of Real-World Error Rates in GPGPU
CCGRID '10 Proceedings of the 2010 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Hi-index | 14.98 |
We present a self-checking detection and diagnosis scheme for transient, delay, and crosstalk faults affecting bus lines of synchronous systems. Faults that are likely to result in the connected logic sampling incorrect bus data are on-line detected. The position of the affected line(s) within the considered bus is identified and properly encoded. The proposed scheme is self-checking with respect to a realistic set of possible internal faults, including node stuck-ats, transistor stuck-ons, transistor stuck-opens, resistive bridgings, transient faults, delays and crosstalks.