Bridging defects resistance in the metal layer of a CMOS process
Journal of Electronic Testing: Theory and Applications
A unified approach for timing verification and delay fault testing
A unified approach for timing verification and delay fault testing
On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines
IEEE Transactions on Computers
Self-Checking Comparator with One Periodic Output
IEEE Transactions on Computers
Compact and Highly Testable Error Indicator for Self-Checking Circuits
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Highly testable and compact single output comparator
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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This paper proposes a distributed two-rail checker architecture which is specifically targeted to self-checking bus-based systems. The architecture makes use of a single bus line to provide error indication. With respect to conventional two-rail checkers additional diagnosing capabilities are provided. The checker is totally-self-checking with respect to stuck-at faults. It features also good self-testing properties with respect to parametric faults, such as bridgings and delay faults.