Low-Cost On-Line Test for Digital Filters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Invariance-Based On-Line Test for RTL Controller-Datapath Circuits
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Finite State Machine Synthesis with Concurrent Error Detection
ITC '99 Proceedings of the 1999 IEEE International Test Conference
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Concurrent Error Detection with Bounded Latency in FSMs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient Concurrent Self-Test with Partially Specified Patterns
Journal of Electronic Testing: Theory and Applications
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We propose a non-intrusive methodology for concurrentfault detection in FSMs. The proposed method is similar toduplication, wherein a replica of the circuit acts as a predictorthat immediately detects potential faults by comparisonto the original FSM. However, instead of duplicatingthe FSM, the proposed method selects a few prediction functionswhich only partially replicate it. Selection is guidedby the objective of minimizing the incurred hardware overheadwithout compromising the ability to detect all faults, yetpossibly introducing fault detection latency. Furthermore, incontrast to concurrent error detection approaches which presumethe ability to re-synthesize the FSM and exploit parity-basedstate encoding, the proposed method does not interferewith the encoding and implementation of the originalFSM. Experimental results indicate that the proposed methodachieves significant hardware overhead reduction over duplication,while detecting more than 99% of all permanentfaults with very low average fault detection latency.