On the generation of small dictionaries for fault location
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Fault dictionary compaction by output sequence removal
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An exact solution to the minimum size test pattern problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Making cause-effect cost effective: low-resolution fault dictionaries
Proceedings of the IEEE International Test Conference 2001
Exclusive Test and its Applications to Fault Diagnosis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Full fault dictionary storage based on labeled tree encoding
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Dynamic diagnosis of sequential circuits based on stuck-at faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Independent Test Sequence Compaction through Integer Programming
ICCD '03 Proceedings of the 21st International Conference on Computer Design
On the Size and Generation of Minimal N-Detection Tests
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Multiple-fault diagnosis based on single-fault activation and single-output observation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Reduced Complexity Algorithm for Minimizing N-Detect Tests
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis
IEEE Transactions on Computers
A Two Phase Approach for Minimal Diagnostic Test Set Generation
ETS '09 Proceedings of the 2009 European Test Symposium
Reduced complexity test generation algorithms for transition fault diagnosis
ICCD '11 Proceedings of the 2011 IEEE 29th International Conference on Computer Design
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diagnosing realistic bridging faults with single stuck-at information
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Creating small fault dictionaries [logic circuit fault diagnosis]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We minimize a given test set without loss of diagnostic resolution in full-response fault dictionary. An integer linear program (ILP), formulated from fault simulation data, provides ultimate reduction of test vectors while preserving fault coverage and pair-wise distinguishability of faults. The complexity of the ILP is made manageable by two innovations. First, we define a generalized independence relation between pairs of faults to reduce the number of fault pairs that need to be distinguished. This significantly reduces the number of ILP constraints. Second, we propose a two-phase ILP approach. In the first phase, using an existing procedure, we select a minimal detection test set. In the second phase, additional tests are selected for the undiagnosed faults using a newly formulated diagnostic ILP. The overall minimized test set may be only slightly longer than a one-step ILP optimization, but has advantages of reducing the minimization problem complexity and the test time required by the minimized tests. Benchmark results show potential for significantly smaller diagnostic test sets.