IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Verilog HDL Primer, Second Edition
A Verilog HDL Primer, Second Edition
Journal of Computer Science and Technology
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An Approach to RTL Fault Extraction and Test Generation
ATS '01 Proceedings of the 10th Asian Test Symposium
High level test generation using data flow descriptions
EURO-DAC '90 Proceedings of the conference on European design automation
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A test evaluation technique for VLSI circuits using register-transfer level fault modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
VLSI testing is being pushed to the high-level based technology. In this paper a Verilog Register transfer level Model (VRM) for integrated circuits is proposed. The model provides a text format file, which is convenient and more practical for developing succeeding Register Transfer Level (RTL) test tools, such as fault simulation, test pattern generation and so forth. Based on the VRM, an RTL concurrent fault simulation approach is presented. After RTL fault models and super faults defined, the concurrent fault simulation algorithm is given. The corresponding RTL concurrent fault simulator, VFSim, was implemented. The initial experiments show that the RTL fault simulator is efficient for VLSI circuits.