Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Low-Energy BIST Design for Scan-based Logic Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test patterns of multiple SIC vectors: theory and application in BIST schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Power in processing cores (microprocessors, DSPs) is primarily consumed in the functional modules of the datapath. Among these modules, multipliers consume the largest amount of power due to their size and complexity. We propose low power BIST schemes for datapath architectures built around multiplier-accumulator pairs, based on deterministic test patterns. Two alternatives are proposed depending on whether the target is low energy dissipation during a BIST session or low power dissipation (i.e. average energy dissipation between successive test vectors). The proposed BIST schemes are more efficient than pseudorandom BIST for the same high fault coverage target. Up to 78.33% energy, saving is achieved by the proposed low energy BIST scheme and up to 82.22% power, saving is achieved by the proposed low power BIST scheme, compared with pseudorandom BIST.