State-Sensitive X-Filling Scheme for Scan Capture Power Reduction

Authors:
Jing-Ling Yang;Qiang Xu
Affiliations:
Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Hong Kong;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2008

Citing 0
Cited 6

On capture power-aware test data compression for scan-based testing

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment

Proceedings of the Conference on Design, Automation and Test in Europe
X-filling for simultaneous shift- and capture-power reduction in at-speed scan-based testing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Suitability of various low-power testing techniques for IP core-based SoC: a survey

VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Weighted transition based reordering, columnwise bit filling, and difference vector: a power-aware test data compression method

VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Scan power reduction for linear test compression schemes through seed selection

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.03

Visualization

Abstract

Based on the operation of a state machine, this paper elucidates a comprehensive frame for probability-based primary-input-dominated X-filling methods to minimize the total weighted switching activity (WSA) during the scan capture operation. Experimental results demonstrate that the proposed approach significantly reduces both average and peak WSAs.