Test Power: a Big Issue in Large SOC Designs

Authors:
Y. Bonhomme;P. Girard;C. Landrault;S. Pravossoudovitch
Affiliations:
-;-;-;-
Venue:
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Year:
2002

Citing 0
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Process-Variation and Temperature Aware SoC Test Scheduling Technique

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Abstract

Test power relates to the power consumed during test of integrated circuits or embedded cores. Test power is now a big concern in large System-on-Chip designs. In this work, we propose to shortly review the state-of-the-art in this domain. We first survey the recent approaches proposed for minimizing test power. Next, we propose some interesting directions for the development of new low power testing techniques by enumerating the relevant criteria that have to be satisfied.