Effects of delay models on peak power estimation of VLSI sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
MD-SCAN Method for Low Power Scan Testing
ATS '02 Proceedings of the 11th Asian Test Symposium
Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
On Reducing Peak Current and Power during Test
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Process variation-aware test for resistive bridges
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
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Modern SoC devices use elaborate power management strategies in functional mode, because not all IP blocks can be functional at the same time. Cost considerations often do not permit overdesigning the power supply infrastructure for test mode or using expensive flip-chip packaging to avoid the problem. Test application must not overexercise the power supply grids, lest the tests damage the device or lead to false test failures. The problem of debugging a delay test failure can therefore be highly complex. The problem is aggravated by on-chip variations in technologies below 100 nm. However, it's possible to avoid false delay test failures by generating safe patterns that are tolerant to on-chip variations. The authors propose a framework for power-safe pattern generation that uses power grid information and regional constraints on switching activity. Experimental results with benchmark circuits demonstrate the effectiveness of this framework.