Interactive presentation: On power-profiling and pattern generation for power-safe scan tests
Proceedings of the conference on Design, automation and test in Europe
Variation-Tolerant, Power-Safe Pattern Generation
IEEE Design & Test
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing
Journal of Electronic Testing: Theory and Applications
Layout-aware, IR-drop tolerant transition fault pattern generation
Proceedings of the conference on Design, automation and test in Europe
NIM: a noise index model to estimate delay discrepancies between silicon and simulation
Proceedings of the Conference on Design, Automation and Test in Europe
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ATPG tools generate test vectors assuming the zero delay modelfor logic gates. In reality, however, gates have finite rise and falldelays that are dependent on process, voltage, and temperaturevariations across different dies on a wafer and within a die. Atest engineer must verify the vectors for timing correctnessbefore they are handed off to the product engineer. Currently,validation of test vectors is done using dynamic simulation of thecircuit using the test vectors. A test vector is invalidated if itcannot reliably distinguish between a good and a faulty circuitunder the signal placement and observation error window of thetester equipment. As chips become faster, the need to test them attheir intended speed of operation has been recognized;accordingly, at-speed functional tests, memory BIST, andtransition delay tests are being used for modern ASICs. Sincestructural tests can result in much more switching activity in thecircuit than what is estimated during normal functioning, theymay fail delay testing due to nanometer effects such as crosstalkand IR drop. As a result, the validation performed by a dynamicsimulation can be prone to error. Here is a case of a test thatover-exercises the chip and declares it faulty even when the chipmay work correctly in functional mode at the intended speed.One solution to this problem is to overdesign, e.g. oversize thepower rails or increase wiring pitch, but this will impact the yieldof the product. We propose layout-aware verification of at-speedtest vectors and eliminating test vectors that can result inmisclassification. Attempting to address this verification indynamic simulation will force the use of circuit simulation ormixed-level simulation techniques, which are expensive in termsof run time. We discuss a static approach to validate the testvectors to save valuable cycle time. Experimental results on twodesigns will be presented to illustrate our approach.