Controlling peak power consumption during scan testing: power-aware DfT and test set perspectives

Authors:
Nabil Badereddine;Patrick Girard;Arnaud Virazel;Serge Pravossoudovitch;Christian Landrault
Affiliations:
Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, LIRMM, Université de Montpellier II / CNRS, Montpellier Cedex 5, France;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, LIRMM, Université de Montpellier II / CNRS, Montpellier Cedex 5, France;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, LIRMM, Université de Montpellier II / CNRS, Montpellier Cedex 5, France;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, LIRMM, Université de Montpellier II / CNRS, Montpellier Cedex 5, France;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, LIRMM, Université de Montpellier II / CNRS, Montpellier Cedex 5, France
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

Citing 6
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Abstract

Scan architectures, though widely used in modern designs for testing purpose, are expensive in power consumption. In this paper, we first discuss the issues of excessive peak power consumption during scan testing. We next show that taking care of high current levels during the test cycle is highly relevant so as to avoid noise phenomena such as IR-drop or Ground Bounce. Next, we discuss a set of possible solutions to minimize peak power during all test cycles of a scan testing process. These solutions cover power-aware design solutions, scan chain stitching techniques and pattern modification heuristics.