Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Error-control coding for computer systems
Error-control coding for computer systems
Using a single input to support multiple scan chains
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
IEEE Design & Test
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Efficient Seed Utilization for Reseeding based Compression
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A Reconfigurable Shared Scan-in Architecture
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Packet-Based Input Test Data Compression Techniques
ITC '02 Proceedings of the 2002 IEEE International Test Conference
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
How Effective are Compression Codes for Reducing Test Data Volume?
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test Vector Compression Using EDA-ATE Synergies
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Changing the Scan Enable during Shift
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
ELF-Murphy Data on Defects and Test Sets
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
An Advanced Fault Isolation System for Digital Logic
IEEE Transactions on Computers
Bit-fixing in pseudorandom sequences for scan BIST
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Survey of Test Vector Compression Techniques
IEEE Design & Test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores
Proceedings of the conference on Design, automation and test in Europe
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan cell positioning for boosting the compression of fan-out networks
Journal of Computer Science and Technology - Special section on trust and reputation management in future computing systmes and applications
Test data compression using alternating variable run-length code
Integration, the VLSI Journal
Masking of X-Values by Use of a Hierarchically Configurable Register
Journal of Electronic Testing: Theory and Applications
Capture-power-aware test data compression using selective encoding
Integration, the VLSI Journal
| Hi-index | 14.98 |
Combinational circuits implemented with exclusive-or gates are used for on-chip generation of deterministic test patterns from compressed seeds. Unlike major test compression techniques, this technique doesn't require test pattern generation with don't cares. Experimental results on industrial designs demonstrate that this new XPAND technique achieves exponential reduction in test data volume and test time compared to traditional scan and significantly outperforms existing test compression tools. The XPAND technique is currently being used by several industrial designs.