Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
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ITC '98 Proceedings of the 1998 IEEE International Test Conference
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FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
ITC '02 Proceedings of the 2002 IEEE International Test Conference
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IEEE Transactions on Computers
Multiple Scan Tree Design with Test Vector Modification
ATS '04 Proceedings of the 13th Asian Test Symposium
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
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ITC '04 Proceedings of the International Test Conference on International Test Conference
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IEEE Design & Test
Optimal Selective Huffman Coding for Test-Data Compression
IEEE Transactions on Computers
Multilevel-Huffman test-data compression for IP cores with multiple scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A test set embedding approach based on twisted-ring counter with few seeds
Integration, the VLSI Journal
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Journal of Electronic Testing: Theory and Applications
A novel x-ploiting strategy for improving performance of test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression based on geometric shapes
Computers and Electrical Engineering
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A unified approach to reduce SOC test data volume, scan power and testing time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ring generators - new devices for embedded test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Growing test data volume and excessive test application time are two serious concerns in scan-based testing for SoCs. This paper presents an efficient test-independent compression technique based on block merging and eight coding (BM-8C) to reduce the test data volume and test application time. Test compression is achieved by encoding the merged blocks after merging consecutive compatible blocks with exact eight codewords. The proposed scheme compresses the pre-computed test data without requiring any structural information of the circuit under test. Therefore, it is applicable for IP cores in SoCs. Experimental results demonstrate that the BM-8C technique can achieve an average compression ratio up to 68.14 % with significant low test application time.