Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs
IEEE Transactions on Computers
Test Data Compression Using Multi-dimensional Pattern Run-length Codes
Journal of Electronic Testing: Theory and Applications
A novel x-ploiting strategy for improving performance of test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding
Journal of Electronic Testing: Theory and Applications
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We present an efficient approach, namely, pattern run-length (PRL) coding, for reducing the volume of test vectors that must be stored in automatic test equipment (ATE) and transferred to each core in a system-on-a-chip (SOC) during manufacturing test. The need for compressing test data is due to the bandwidth bottleneck between the ATE and the SOC. In our new coding scheme, the test vectors for the SOC are stored in compressed form in the ATE memory and transferred to the chip. An embedded processor is employed to perform decompression. The decompressed test set is then applied to the scan chains of each core-under-test. Pattern run-length coding works by compressing consecutive patterns in an innovative manner. The proposed compression is data-independent. The program for decompression is very small and simple, thereby allowing fast and high throughput to minimize test time. Experimental results for ISCAS-89 benchmarks show that for almost all of the circuits our new technique results in much better compression ratios than former methods.