Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Design for Test: For Digital Integrated Circuits
Design for Test: For Digital Integrated Circuits
On Adaptive Strategies for an Extended Family of Golomb-Type Codes
DCC '97 Proceedings of the Conference on Data Compression
Test Data Compression Using Don't-Care Identification and Statistical Encoding
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs
Proceedings of the conference on Design, automation and test in Europe
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Test Power Reduction with Multiple Capture Orders
ATS '04 Proceedings of the 13th Asian Test Symposium
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Two efficient methods to reduce power and testing time
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Low Power Test Compression Technique for Designs with Multiple Scan Chain
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Frugal linear network-based test decompression for drastic test cost reductions
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction
ITC '04 Proceedings of the International Test Conference on International Test Conference
DATA COMPRESSION FOR MULTIPLE SCAN CHAINS USING DICTIONARIES WITH CORRECTIONS
ITC '04 Proceedings of the International Test Conference on International Test Conference
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Low-power scan testing and test data compression for system-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On reducing test power and test volume by selective pattern compression schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supply the test patterns either through the compressed scan chain whose scanned values will be decoded to the original scan cells, or directly through the original scan chain using minimum transition filling method. Due to shorter length of a compressed scan chain, the potential switching activities and the required storage bits can be both reduced. Furthermore, the proposed scheme also supports multiple scan chains. The experimental results demonstrate that, with few hardware overhead, the proposed scheme can achieve significant improvement in shift-in power reduction and large amount of test data volume reduction.