ATPG for heat dissipation minimization during scan testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
NRG: global and detailed placement
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Design for Test: For Digital Integrated Circuits
Design for Test: For Digital Integrated Circuits
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A new approach to scan chain reordering using physical design information
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Power Driven Chaining of Flip-Flops in Scan Architectures
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction
ITC '04 Proceedings of the International Test Conference on International Test Conference
Layout driven synthesis of multiple scan chains
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A selective pattern-compression scheme for power and test-data reduction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
On reducing test power and test volume by selective pattern compression schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC design, circuit testability becomes one of the most challenging works. Without careful design in scan cell placement and chain ordering, circuits consume much more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this paper, we present an approach to simultaneously minimizing power and routing cost in scan chain reordering after cell placement. We formulate the problem as a Traveling Salesman Problem (TSP), different cost evaluation from [3], [5], and apply an efficient heuristic to solve it. The experimental results are encouraging. Compared with a recent result in [3], which uses the approach with clustering overhead, we obtain up to 10% average power saving under the same low routing cost. Furthermore, we obtain 57% routing cost improvement under the same test power consumption in s9234, one of ISCAS'89 benchmarks. We collaborate multiple scan chains architecture with our methodology and obtain good results as well.