Low Power Test Compression Technique for Designs with Multiple Scan Chain

Authors:
Youhua Shi;Nozomu Togawa;Masao Yanagisawa;Tatsuo Ohtsuki;Shinji Kimura
Affiliations:
Waseda University, Japan;Waseda University, Japan;Waseda University, Japan;Waseda University, Japan;Grad. School of Infomation, Production and Systems, Waseda University, Japan
Venue:
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Year:
2005

Citing 0
Cited 3

A multilayer data copy test data compression scheme for reducing shifting-in power for multiple scan design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A selective pattern-compression scheme for power and test-data reduction

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
On reducing test power and test volume by selective pattern compression schemes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a new DFT technique that can significantly reduce test data volume as well as scan-in power consumption for multiscan-based designs. It can also help to reduce test time and tester channel requirements with small hardware overhead. In the proposed approach, we start with a pre-computed test cube set and fill the don't-cares with proper values for joint reduction of test data volume and scan power consumption. In addition we explore the linear dependencies of the scan chains to construct a fanout structure only with inverters to achieve further compression. Experimental results for the larger ISCAS'89 benchmarks show the efficiency of the proposed technique.