On Reducing Peak Current and Power during Test
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
Scan-Based Tests with Low Switching Activity
IEEE Design & Test
Journal of Electronic Testing: Theory and Applications
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations
Journal of Electronic Testing: Theory and Applications
Scan chain clustering for test power reduction
Proceedings of the 45th annual Design Automation Conference
Dynamic scan chain partitioning for reducing peak shift power during test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
Journal of Electronic Testing: Theory and Applications
On reducing scan shift activity at RTL
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Defect aware X-filling for low-power scan testing
Proceedings of the Conference on Design, Automation and Test in Europe
Reducing the switching activity of test sequences under transparent-scan
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A new scheme of test data compression based on equal-run-length coding (ERLC)
Integration, the VLSI Journal
Implementation of gating technique with modified scan flip-flop for low power testing of VLSI chips
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Low-power skewed-load tests based on functional broadside tests
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power test sets under test-related primary input constraints
International Journal of Critical Computer-Based Systems
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This paper presents a test vector modification method for reducing power dissipation during test application for a full-scan circuit. The method first identifies a set of don't care (X) inputs of given test vectors, to which either logic value 0 or 1 an be assigned without losing fault coverage. Then, the method reassigns logic values to the X inputs so as to decrease switching activity of the circuit during scan shifting. Experimental results for benchmark circuits show the proposed method could decrease switching activity of a given test set to 48% of the original test set.