Scan-Based Tests with Low Switching Activity

Authors:
Santiago Remersaro;Xijiang Lin;Sudhakar M. Reddy;Irith Pomeranz;Janusz Rajski
Affiliations:
University of Iowa;Mentor Graphics;University of Iowa;Purdue University;Mentor Graphics
Venue:
IEEE Design & Test
Year:
2007

Citing 9
Cited 3

Adapting Scan Architectures for Low Power Operation

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Vector Modification for Power Reduction during Scan Testing

VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist

ITC '99 Proceedings of the 1999 IEEE International Test Conference
On the generation of scan-based test sets with reachable states for testing under functional operation conditions

Proceedings of the 41st annual Design Automation Conference
On Low-Capture-Power Test Generation for Scan Testing

VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
On Reducing Peak Current and Power during Test

ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques

ITC '04 Proceedings of the International Test Conference on International Test Conference
Constraint extraction for pseudo-functional scan-based delay testing

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Low Shift and Capture Power Scan Tests

VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems

On systematic illegal state identification for pseudo-functional testing

Proceedings of the 46th Annual Design Automation Conference
Defect aware X-filling for low-power scan testing

Proceedings of the Conference on Design, Automation and Test in Europe
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects

Proceedings of the Conference on Design, Automation and Test in Europe

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Abstract

Supply current and power dissipation during scan-based test can be far higher than during normal circuit operation, owing to excessive switching activity caused by the tests. Excessive switching activity can occur during scan shift and test response capture. Higher peak-current demands can cause supply voltage droops, making good chips fail at-speed tests. Higher average switching activity causes higher power dissipation and chip temperature, which in turn can cause hot spots and damage circuits under test. This article investigates a method to derive tests with reduced switching activity during scan shift and test response capture. The method does not require additional hardware or modifications to the scan chains. The authors present experimental results on benchmark and industrial circuits.