Power Reduction in Test-Per-Scan BIST
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Test Vector Modification for Power Reduction during Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Modified Scan Flip-Flop for Low Power Testing
ATS '10 Proceedings of the 2010 19th IEEE Asian Test Symposium
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power design using double edge triggered flip-flops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a technique to reduce the power of combinational circuits during testing. Power dissipation of IC during test mode is greater than the IC's normal mode of functioning. During testing a significant fraction of test power is dissipated in the combinational circuits. To reduce the test power we proposed a modified structure of scan flip-flop in our previous work. In this paper we present the two possible gating techniques for the modified scan flip-flop to reduce the power dissipation due to unnecessary switching of combinational circuits too. The proposed method is implemented in some of the ISCAS benchmark circuits to observe the percentage of power saving after applying the gating technique. The result of our experiment shows that, about 13%-18.5% more power saving in addition to the proposed scan flip-flop.