Double-Edge-Triggered Flip-Flops
IEEE Transactions on Computers
Analysis of double edge triggered clocked storage elements
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
Implementation of gating technique with modified scan flip-flop for low power testing of VLSI chips
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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In this paper we study the power savings possible using double edge triggered (DET), instead of, conventional single edge triggered (SET) flip-flops. We begin the paper by introducing a set of novel D-type double edge triggered flip-flops which can be implemented with fewer transistors than any previous design. The power dissipation in these flip-flops and single edge triggered flip-flops is compared via architectural level studies, analytical considerations and simulations. The analysis includes an implementation independent study on, the effect of input sequences, in the energy dissipation of single and double edge triggered flip-flops. The system level energy savings possible by using registers consisting of double edge triggered flip-flops, instead of single edge triggered flip-flops, is subsequently explored. The results are extremely encouraging, indicating that double edge triggered flip-flops are capable of significant energy savings, for only a small overhead in complexity.