Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics)
Structural Simplification and Decomposition of Asynchronous Sequential Circuits
IEEE Transactions on Computers
Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
Low power design using double edge triggered flip-flops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reconfigurable clock polarity assignment flow for clock gated designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A conventional positive-edge-triggered flip-flop (FF) senses and responds to the control input or inputs at the time the clock input is changing from 0 to 1. It does not respond at all to changes in the opposite direction. Negative-edge-triggered FF's behave in a complementary manner. Thus, these FF's can respond at most once per clock pulse cycle. It is proposed that double-edge-triggered (DET) FF's, responding to both edges of the clock pulse would have advantages with respect to speed and energy dissipation.