Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
Combining low-power scan testing and test data compression for system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
High Defect Coverage with Low-Power Test Sequences in a BIST Environment
IEEE Design & Test
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
A token scan architecture for low power testing
Proceedings of the IEEE International Test Conference 2001
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Power Driven Chaining of Flip-Flops in Scan Architectures
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores
ATS '01 Proceedings of the 10th Asian Test Symposium
Reducing Power Dissipation during Test Using Scan Chain Disable
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Test Power Reduction through Minimization of Scan Chain Transitions
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test Vector Modification for Power Reduction during Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Controlling Peak Power During Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Low Power Test Data Compression Based on LFSR Reseeding
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
On Low-Capture-Power Test Generation for Scan Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Jump Scan: A DFT Technique for Low Power Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
Low-power scan testing and test data compression for system-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An automatic test pattern generator for minimizing switching activity during scan testing activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LT-RTPG: a new test-per-scan BIST TPG for low switching activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis
IEEE Design & Test
Scan chain clustering for test power reduction
Proceedings of the 45th annual Design Automation Conference
Test strategies for low power devices
Proceedings of the conference on Design, automation and test in Europe
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
QC-fill: quick-and-cool X-filling for multicasting-based scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power supply noise reduction for at-speed scan testing in linear-decompression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power test in compression-based reconfigurable scan architectures
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Defect aware X-filling for low-power scan testing
Proceedings of the Conference on Design, Automation and Test in Europe
QC-fill: an X-fill method for quick-and-cool scan test
Proceedings of the Conference on Design, Automation and Test in Europe
On reducing test power and test volume by selective pattern compression schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The paper presents a novel low power test scheme integrated with the embedded deterministic test environment. It reduces significantly switching rates in scan chains with minimal hardware modification. Experimental results obtained for industrial circuits clearly indicate that switching activity can be reduced up to 150 times along with improved compression ratios.