A study of hardware design and overhead in Built-in-Self-Testable UART
WISICT '04 Proceedings of the winter international synposium on Information and communication technologies
Low-power weighted pseudo-random BIST using special scan cells
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Software-based self-test methodology for crosstalk faults in processors
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Efficient scan-based BIST scheme for low power testing of VLSI chips
Proceedings of the 2006 international symposium on Low power electronics and design
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
A BIST TPG for low power dissipation and high fault coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power problems in VLSI circuit testing
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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This paper presents a low hardware overhead test pattern generator (TPG) for scan-based BIST that can reduce switching activity in CUTs during BIST and also achieve very high fault coverage with a reasonable length of test sequence. Since the correlation between consecutive vectors applied to a circuit during BIST is significantly lower, switching activity in the circuit can be significantly higher during BIST than that during its normal operation. Excessive switching activity during test application can damage CUTs during BIST. The proposed BIST decreases the number of transitions that occur at scan inputs during scan shift operations and hence decreases switching activity during BIST. The proposed BIST is comprised of two TPGs: LT RTPG and 3-weight WRBIST TPG, both of which are proposed in previous publications. This paper shows that the 3-weight WRBIST TPG, which is used to detect random pattern resistant faults, can also be used to reduce switching activity in CUTs during BIST. Test patterns generated by the LT RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST TPG detect faults that remain undetected after LT RTPG patterns are applied. The proposed BIST TPG does not require modification of mission logics, which can entail performance degradation. Experimental results for ISCAS 89 benchmark circuits demonstrate that the proposed BIST can significantly reduce switching activity during BIST while achieving 100% fault coverage for all benchmark circuits. Larger reduction in switching activity is achieved in large circuits. Experimental results also showthat the proposed BIST can be implemented with very low area overhead.