Extending OPMISR beyond 10x Scan Test Efficiency
IEEE Design & Test
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
ITC '04 Proceedings of the International Test Conference on International Test Conference
X-Masking During Logic BIST and Its Impact on Defect Coverage
ITC '04 Proceedings of the International Test Conference on International Test Conference
Channel Masking Synthesis for Efficient On-Chip Test Compression
ITC '04 Proceedings of the International Test Conference on International Test Conference
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This article presents a two-stage test response compactor with scan selection logic and an on-chip compare-and-response collector. This compactor is capable of handling a wide range of X state profiles, offers compression far higher than the ratio of scan chains to compactor outputs, and provides excellent diagnostic resolution.