Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Inserting Test Points to Control Peak Power During Scan Testing
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Partial Gating Optimization for Power Reduction During Test Application
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DS-LFSR: a BIST TPG for low switching activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gating internal nodes to reduce power during scan shift
Proceedings of the 20th symposium on Great lakes symposium on VLSI
On reducing scan shift activity at RTL
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fixed-state tests for delay faults in scan designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-safe application of tdf patterns to flip-chip designs during wafer test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this paper, we show that not every scan cell contributes equally to the power consumption during scan-based test. The transitions at some scan cells cause more toggles at the internal signal lines of a circuit than the transitions at other scan cells. Hence the transitions at these scan cells have a larger impact on the power consumption during test application. We call these scan cells power sensitive scan cells. A signal probability based approach is proposed to identify a set of power sensitive scan cells. Additional hardware is added to freeze the outputs of power sensitive scan cells during scan shifting in order to reduce the shift power consumption. Experimental results on industrial circuits show that on average more than 45% of the scan shift power can be eliminated when freezing only 5% of power sensitive scan cells.