ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
A critical-path-aware partial gating approach for test power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells
Journal of Electronic Testing: Theory and Applications
Efficient partial scan cell gating for low-power scan-based testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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It is a common practice to gate a limited number of scan cells in order to reduce overall switching activity during shift, thereby, reducing the circuit's dynamic power consumption. In this paper, we propose a novel approach to reduce overall shift power during test by inserting extra hardware at the output of scan cells and internal gates. Based on the estimated dynamic power (using PrimeTime-PX), the proposed approach uses a linear time algorithm to identify the nodes to be gated. To avoid degrading the timing of the circuit, additional logic is added only at paths that are not timing-critical. The proposed approach significantly outperforms all approaches that gate only scan cells. Experimental results on ISCAS and ITC benchmarks show that on average more than 48% of the dynamic power can be reduced while reducing the hardware overhead by up to 3.75X.