Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Automatic sizing of power/ground (P/G) networks in VLSI
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Optimum design of reliable IC power networks having general graph topologies
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Vector generation for maximum instantaneous current through supply lines for CMOS circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Gate-level power and current simulation of CMOS integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Estimation of maximum current envelope for power bus analysis and design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A floorplan-based planning methodology for power and clock distribution in ASICs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
Simulation and optimization of the power distribution network in VLSI circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Static Verification of Test Vectors for IR Drop Failure
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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This paper presents a new input-independent method for finding the maximum voltage drop of power bus in digital VLSI circuits. The method relies on expressing the voltage at the power bus nodes in terms of gate currents using sensitivity analysis. Circuit timing information and circuit functionality are used to find maximum simultaneous switching and upper bounds on maximum voltage drop at a given node over a clock cycle. The effects of primary inputs(PIs) misalignment and statistical variation in the circuit delays on maximum voltage drop are automatically included in our method. HSPICE exhaustive simulation results on 3 by 3 and 4 by 4 multiplier are used to validate our work.