Modeling Power Supply Noise in Delay Testing

Authors:
Jing Wang;Duncan M. (Hank) Walker;Xiang Lu;Ananta Majhi;Bram Kruseman;Guido Gronthoud;Luis Elvira Villagra;Paul J. A. M. van de Wiel;Stefan Eichenberger
Affiliations:
Texas A&M University;Texas A&M University;P.A. Semi;NXP Semiconductors;NXP Semiconductors;NXP Semiconductors;NXP Semiconductors;NXP Semiconductors;NXP Semiconductors
Venue:
IEEE Design & Test
Year:
2007

Citing 9
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Abstract

Excessive power supply noise can affect path delay in ICs. Silicon results show that filling of don't-care bits in test patterns can cause as much as 15% delay variation. Such extra delay may cause overkill during delay test. This article describes two types of low-cost noise models, compares them in model accuracy and application, and provides directions for model improvement. Excessive noise may come from compaction or filling during delay test generation. Experiments show how noise varies with different filling approaches, and how compaction is affected when the noise level for compacted tests is constrained.