Proceedings of the 37th Annual Design Automation Conference
Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources
Proceedings of the 37th Annual Design Automation Conference
Fast power/ground network optimization based on equivalent circuit modeling
Proceedings of the 38th annual Design Automation Conference
Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Area minimization of power distribution network using efficient nonlinear programming techniques
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Random walks in a supply network
Proceedings of the 40th annual Design Automation Conference
Power network analysis using an adaptive algebraic multigrid approach
Proceedings of the 40th annual Design Automation Conference
Power grid reduction based on algebraic multigrid principles
Proceedings of the 40th annual Design Automation Conference
Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Hierarchical analysis of power distribution networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a hierarchical relaxed approach to analyze large scale on-chip power/ground (P/G) grids with C4 packages efficiently. Different from the existing hierarchical approach where macro models and time-consuming matrix density reduction technique are used, this novel approach uses an iterative relaxation procedure to explicitly exploit the character of boundary nodes caused by C4 bumps, which can lead to more speedup without losing any accuracy. Also, an efficient partition strategy is generated to help the new algorithm to achieve higher performance on C4 based P/G grid. Experimental results demonstrate that the new algorithm is as accurate as the existing hierarchical method while it delivers more speedup over it for C4 based P/G grid.