Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A floorplan-based planning methodology for power and clock distribution in ASICs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Integrated power supply planning and floorplanning
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Fast power/ground network optimization based on equivalent circuit modeling
Proceedings of the 38th annual Design Automation Conference
On-chip power supply network optimization using multigrid-based technique
Proceedings of the 40th annual Design Automation Conference
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Efficient power/ground network analysis for power integrity-driven design methodology
Proceedings of the 41st annual Design Automation Conference
Optimal planning for mesh-based power distribution
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Floorplan and power/ground network co-synthesis for fast design convergence
Proceedings of the 2006 international symposium on Physical design
Heuristic power/ground network and floorplan co-design method
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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As technology advances, the voltage (IR) drop in the Power/Ground (P/G) network becomes a serious problem in modern IC design. The P/G network co-design with floorplan can improve the power design quality. Different with traditional approaches which analyze P/G network during the floorplanning iterations, in this paper, an efficient pattern selection method is used to provide gradient information for fast signal-integrity estimation. We also propose a novel P/G aware incremental algorithm which can intelligently fix the violations during the floorplanning process. The P/G pin assignment and wire sizing method are adopted during the floorplanning process so that the power routing resource can be minimized with the constraints of IR drop and electron migration (EM) considered. Experimental results based on the MCNC benchmarks show that our design not only significantly speeds up the optimization process, but also optimizes the power routing resource while the quality of the floorplanning is maintained.