An automated design of minimum-area IC power/ground nets
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Laying the power and ground wires on a VLSI chip
DAC '83 Proceedings of the 20th Design Automation Conference
Computation of power supply nets in VLSI layout
DAC '81 Proceedings of the 18th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Multi-pad power/ground network design for uniform distribution of ground bounce
DAC '98 Proceedings of the 35th annual Design Automation Conference
Thermal and Power Integrity Based Power/Ground Networks Optimization
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Topology optimization of structured power/ground networks
Proceedings of the 2004 international symposium on Physical design
A fast algorithm for power grid design
Proceedings of the 2005 international symposium on Physical design
An integer-linear-programming-based routing algorithm for flip-chip designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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An algorithm is presented for obtaining a planar routing of two power nets in building-block layout. In contrast to other works, more than one pad for each of the power nets is allowed. First, conditions are established to guarantee a planar routing. The algorithm consists of three parts, a top-down terminal clustering, a bottom-up topological path routing and a wire width calculation procedure. Because of the hierarchical nature of the algorithm, it is inherently fast.